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The decoder in EU translates instructions fetched from memory into a series of actions, which the EU carries out. Give the register classification of The contains: i. General purpose registers: They are used for holding data, variables and intermediate results temporarily. They are used as segment registers, pointers, index register or as offset storage registers for particular addressing modes. What are general data registers?

AX register is used as bit accumulator. BX register is used as offset storage for forming physical addresses in case of certain addressing modes.

CX register is used as a default counter in case of string and loop instructions. DX register is used as an implicit operand or destination in case of a few instructions. Give the different segment registers. The four segment registers are: i. Code segment register: It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.

Data segment register: It points to the data segment of the memory, where data is resided. Extra segment register: It also contains data. Stack segment register: It is used for addressing stock segment of memory.

It is used to store stack data. What are pointers and index registers? IP, BP and SP are the pointers and contain offsets within the code, data and stack segments respectively. SI and DI are the index registers, which are used as general purpose registers and also for offset storage in case of indexed, based indexed and relative based indexed addressing modes.

How is the physical address calculated? Give an example. The physical address, which is bits long is calculated using the segment and offset registers, each bits long.

The segment address is shifted left bit-wise four times and offset address is added to this to produce a 20 bit physical address. What is pre-decoded instruction byte queue? To make use of the external bus when the processor internally executes the instruction, the external bus is used to fetch the machine code of the next instruction and arrange it in a queue called as pre-encoded instruction byte queue.

What is meant by memory segmentation? Memory segmentation is the process of completely dividing the physically available memory into a number of logical segments. Each segment is 64K byte in size and is addressed by one of the segment register. What are the advantages of segmented memory? The advantages of segmented memory are: i. Allows the memory capacity to be 1Mbyte, although the actual addresses to be handled are of bit size. Allows the placing of code, data and stack portions of the same program in different parts of memory for data and code protection.

What is pipelining? Fetching the next instruction while the current instruction executes is called pipelining. What are the two parts of a flag register? The two parts of the 16 bit flag register are: i. Condition code or status flag register: It consists of six flags to indicate some condition produced by an instruction.


Machine control flag register: It consists of three flags and are used to control certain operations of the processor. Draw the format of flag register. Explain the three machine control flags. Trap flag: If this flag is set, the processor enters the single step execution.

If this flag is set, the markable interrupts are recognized by the CPU, otherwise they are ignored. Direction flag: This is used by string manipulation instructions. Otherwise, the string is processed from highest address to lowest address, i.

Draw the pin configuration of What are the three groups of signals in ? The signals are categorized in three groups. They are: i. The signals having common functions in minimum and maximum mode. The signals having special functions for minimum mode. The signals having special functions for maximum mode. What are the uses of AD15 — AD0 lines? Address remains on the lines during T1 state, while data is available on data bus during T2, T3, Tw and T4 states.

These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. What is the operation of RD signal? RD is an active low signal. Give the function of i. Ready and ii. INTR signal.

Ready signal: It is an acknowledgement from slow devices of memory that they have completed data transfer. The signal is synchronized by A clock generator to give ready input to The signal is active high. INTR signal: It is a level triggered input.

This is sampled during the last cycle of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resetting the interrupt enable flag. The signal is active high and internally synchronized. What is the operation performed when TEST input is low? When the TEST input is low, execution will continue, else, the processor remains in an idle state.

NMI is an edge-triggered input, which causes a type 2 interrupt. It is not maskable internally by software and transition from low to high initiates the interrupt response at the end of the current instruction.

This input is internally synchronized. What is the purpose of clock input? The clock input provides the basic timing for processor operation and bus control activity. The range of frequency varies from 5MHz to 10MHz.

It must be active for atleast four clock cycles. It is internally synchronized. The request occurs on or before T2 state of the current cycle. The current cycle is not operating over the lower byte of a word.

The current cycle is not the first acknowledge of an interrupt acknowledge sequence. A lock instruction is not being executed. Differentiate between minimum and maximum mode. Minimum mode Maximum mode i. All the control signals are given out by The processor derive the status signals S2 , S1 and S0.

Another chip called bus controller derives control signals using this status information. There is a single microprocessor. There may be more than one microprocessor. Give any four pin definitions for the minimum mode. Symbol Description i. INTA Indicates recognition of an interrupt request.

Consists of two negative going pulses in two consecutive bus cycles. ALE Outputs a pulse at the beginning of the bus cycle and to indicate an address available on address pins.

HLDA Outputs a bus grant to a requesting master. HOLD Receives bus requests from bus masters. What is a bootstrap loader?

This location would be in read-only section of memory and contains a JMP instruction to a program for initializing the system and loading the operating system. Such a program is called as a bootstrap loader.

What are the pins that are used to indicate the type of transfer in minimum mode? What is the operation of S0, S1 and S2 pins in maximum mode? S2, S1, S0 indicates the type of transfer to take place during the current bus cycle. Give any four pin definitions for maximum mode. This status indicates the activity in the queue during the previous clock cycle. LOCK Indicates that the bus is not to be relinquished to other potential bus masters.

Draw the bus request and bus grant timings in minimum mode system. Write a program to add a data byte located at offset H in H segment to another data byte available at H in the same segment and store the result at H in the same segment. What is the main use of LOCK prefix?

The lock prefix allows a microprocessor to make sure that another processor does not take control of the system bus while it is in the middle of a critical instruction which uses the system bus. What are the different types of addressing modes of instruction set? The different addressing modes are: i. Immediate ii. Direct iii. Register iv. Register indirect v.

Indexed vi. Register relative vii. Based indexed viii.

Relative based indexed What are the different types of instructions in microprocessor? The different types of instructions in microprocessor are: i. Arithmetic and logical instructions iii.

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Branch instructions iv. Loop instruction v. Machine control instruction vi. Flag manipulation instruction vii. Shift and rotate instruction viii. String instruction. What is multiple interrupt processing capability? Whenever a number of devices interrupt a CPU at a time, and id the processor is able to handle them properly, it is said to have multiple interrupt processing capability.

What is hardware interrupt? An interrupt can come from any one of three sources. An interrupt caused by the signal applied to one of these input is referred to as a hardware interrupt. What is software interrupt? The interrupt caused due to execution of interrupt instruction is called software interrupt. What is assembly level programming? The object code modules are further converted into executable code using linker and loader programs.

This type of programming is called assembly level programming. What is a stack?

Stack is a top-down data structure, whose elements are accessed using a pointer that is implemented using the SS and SP registers. It is a LIFO data segment. How is the stack top address calculated? The stack top address is calculated using the contents of the SS and SP register.

The contents of stack segment SS register is shifted left by four bit positions multiplied by 0h and the resulted bit content is added with the bit offset value of the stack pointer SP register.

What are the two types of interrupts in ? The two types of interrupts are: i. External interrupts: In this, the interrupt is generated outside the processor. Example : Keyboard interrupt. Internal interrupts: It is generated internally by the processor circuit or by the execution of an interrupt instruction. Example : Zero interrupt, overflow interrupt.

The accumulator registers A and B at addresses OEOh and OFOh, respectively are used to store temporary values and the results of arithmetic operations. Program status word PSW is the set of flags that contains the status information and is considered as one of the special function register.

It is defined anywhere in the on- chip byte RAM. It is allotted an address in the special function register bank. The other is a receive buffer, which is a serial-in parallel-out register. Timer registers are two bit registers and can be accessed as their lower and upper bytes. TLO represents the lower byte of the timing register 0, while THO represents higher bytes of the timing register 0.

These registers can be accessed using the four addresses allotted to them, which lie in the special function registers address range, i. Timing and control unit is used to derive all the necessary timing and control signals required for the internal operation of the circuit. It also derives control signals that are required for controlling the external system bus. Oscillator circuit is used to generate the basic timing clock signal for the operation of the circuit using crystal oscillator.

Instruction register is used for the purpose of decoding the opcode of an instruction to be executed and gives information to the timing and control unit generating necessary signals for the execution of the instruction.

The signal is valid only for external memory accesses. One ALE pulse is skipped during each access to external data memory. The two power saving modes of operation are: I. Idle mode: In this mode, the oscillator continues to run and the interrupt, serial port and timer blocks are active, but the clock to the CPU is disabled. The CPU status is preserved. This mode can be terminated with a hardware interrupt or hardware reset signal.

After this, the CPU resumes program execution from where it left off. Power down mode: In this mode, the on-chip oscillator is stopped. All the functions of the controller are held maintaining the contents of RAM.

In stores the programs to be executed. It stores only program code which is to be executed and thus it need not be written, so it is implemented using EPROM It stores the data, line intermediate results, variables and constants required for the execution of the program.

The data memory may be read from or written to and thus it is implemented using RAM.

There are six addressing modes in The operands are specified using the 8-bit address field, in the instruction format. This is known as direct addressing mode. Eg: Mov R0, 89H In this mode, the 8-bit address of an operand is stored in a register and the register, instead of the 8-bit address, is specified in the instruction. The registers R0 and R1 of the selected bank of registers or stack pointer can be used as address registers for storing the 8-bit addresses.

The operations are stored in the registers R0 — R7 of the selected register bank. One of these eight registers R0 — R7 is specified in the instruction using the 3-bit register specification field of the opcode format. A register bank can be selected using the two bank select bits of the PSN. In this type of instructions, the operand is implicitly specified using one of the registers. Some of the instructions always operate only on a specific register.

Eg: RLA; This instruction rotates accumulator left. An immediate data ie. For specifying a hex number, it should be followed by H. These are known as immediate addressing mode. This addressing mode is used only to access the program memory. It is accomplished in for look-up table manipulations. Program counter or data pointer are the allowed bit address storage registers, in this mode of addressing. These bit registers point to the base of the look-up table and the ACC register contains a code to be converted using the look-up table.

The look-up table data address is found out by adding the contents of register ACC with that of the program counter or data pointer. In case of jump instruction, the contents of accumulator are added with one of the specified bit registers to form the jump destination address.

Encapsulation is a method used to protect the chip and the interconnect technology used the chip electrically to the printer circuit card.

The transistor will be off and the pin will float and can be driven by the external circuit. The dotted-AND bus is a bus that utilizes a number of transistors pulling down line to ground using open collectors or open drain.

The bus is pulled-up with a number of transistors, controlled by a control signal, any of which can pull the line low. The few rules that have to be followed are: i. Only use negatively active signals ii. If a pin is not actively outputting a signal, set it high. The gate is a secondary execution control bit. If the gate bit is reset, the timer is enabled to run at any time. If the bit is set, then only when appropriate-INTn bit is high, the timer will run. The timer overflow bits are set when timer rolls over and reset either by the execution of an ret instruction or by software, manually clearing the bits.

When the timer reaches the limits of the count, the overflow flag is set and the counter is reset back to zero. The two different modes in which Timer 2 operates are. Capture mode Timer 2 operates as free running clocks, which saves the timers value on each high to low transition. It can be used for recording bit lengths when receiving Manchester-encoded data. This feature is used to implement a system watch dog timer.

A watching timer is used to protect an application in case the controlling microcontroller begins to run amok and execute randomly rather than the preprogrammed instructions written for the application. Interrupt is defined as request that can be refused. If not refused and when an interrupt request is acknowledged, a special set of routine or events are followed to handle the interrupt. The steps followed are: I.

Save the context register information. Reset the hardware requesting the interrupt. Reset the interrupt controller. Process the interrupt. Restore the context information. Return to the previously executing code. There are five different ways to interrupt Two of these are from external electrical signals.

The two different electrical signals that cause an interrupt are: I. Logic — 0 to Logic — 1 change known as transition activated interrupt.

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Logic 0, Level activated interrupt. EA: Disables all interrupts Es: Enables or disable the serial port interrupt. ET1: Enable or disable the timer 1 overflow interrupt. EX1: Enable or disable external interrupt 1. ET0: Enable or disable the timer 0 overflow interrupt. EX0: Enable or disable external interrupt 0. Nesting of interrupts means that interrupts are re-enabled inside an interrupt handler. If another interrupt request codes in, while the first interrupt handler is executing, processor execution will acknowledge the new interrupt and jump to its vector.

The serial port is a very complex peripheral and able to send data synchronously and asynchronously in a variety of different transmission modes.

In synchronous mode mode 0 , the instruction clock is used. An application for synchronous serial communication is RS — In , during execution the data is fetched continuous. When an address is outside the internal control store, an external memory access is generated. To protect the code from others, the output data is XORed with the value in a byte portion in EPROM that is used to scramble what is read back after programming.

Macros are small routines that are used to replace strings in the program. If a label within a macro is not declared local, then at assembly time, there will be two types of errors: I. The first will state that there are multiple labels in the source. The subroutine can be located after the interrupt handlers or between variable initialization ant the mainline code. The location of the subroutine is location of the subroutine is largely arbitrary. Interpreters and compilers convert high-level language statements directly into processor instructions without the programmer being involved.

They are used in the field of: I.

Closed — loop control. Modems III. Printers IV. Disk drives V. Medical instrumentation. The various ways of accessing data are called addressing modes. The five addressing modes are, I. Immediate addressing II. Register addressing III.

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Direct addressing IV. Register indirect addressing a. Indexed addressing. In immediate addressing mode, the source operand is constant. In this mode, as the name implies, when the instruction is assembled, the operand comes immediately after the opcode. Register addressing mode involves the use of register to hold data to be manipulated. But movement of data between Rn register is not allowed. The following two points should be noted SFR addresses.

Other specialized units exist for video processing and machine vision. See: Hardware acceleration. Microcontrollers integrate a microprocessor with peripheral devices in embedded systems. Systems on chip SoCs often integrate one or more microprocessor or microcontroller cores. Speed and power considerations[ edit ] Microprocessors can be selected for differing applications based on their word size, which is a measure of their complexity.

Longer word sizes allow each clock cycle of a processor to carry out more computation, but correspond to physically larger integrated circuit dies with higher standby and operating power consumption. Where a system is expected to handle larger volumes of data or require a more flexible user interface, 16, 32 or 64 bit processors are used.

An 8- or bit processor may be selected over a bit processor for system on a chip or microcontroller applications that require extremely low-power electronics , or are part of a mixed-signal integrated circuit with noise-sensitive on-chip analog electronics such as high-resolution analog to digital converters, or both.

Running bit arithmetic on an 8-bit chip could end up using more power, as the chip must execute software with multiple instructions.

Such products as cellular telephones, DVD video system and HDTV broadcast systems fundamentally require consumer devices with powerful, low-cost, microprocessors. Increasingly stringent pollution control standards effectively require automobile manufacturers to use microprocessor engine management systems to allow optimal control of emissions over the widely varying operating conditions of an automobile. Non-programmable controls would require complex, bulky, or costly implementation to achieve the results possible with a microprocessor.

A microprocessor control program embedded software can be easily tailored to different needs of a product line, allowing upgrades in performance with minimal redesign of the product. Different features can be implemented in different models of a product line at negligible production cost. Microprocessor control of a system can provide control strategies that would be impractical to implement using electromechanical controls or purpose-built electronic controls.

For example, an engine control system in an automobile can adjust ignition timing based on engine speed, load on the engine, ambient temperature, and any observed tendency for knocking—allowing an automobile to operate on a range of fuel grades. History[ edit ] The advent of low-cost computers on integrated circuits has transformed modern society. General-purpose microprocessors in personal computers are used for computation, text editing, multimedia display , and communication over the Internet.

Many more microprocessors are part of embedded systems , providing digital control over myriad objects from appliances to automobiles to cellular phones and industrial process control. The first use of the term "microprocessor" is attributed to Viatron Computer Systems [5] describing the custom integrated circuit used in their System 21 small computer system announced in By the late s, designers were striving to integrate the central processing unit CPU functions of a computer onto a handful of very-large-scale integration metal-oxide semiconductor chips, called microprocessor unit MPU chipsets.

Building on an earlier Busicom design from , Intel introduced the first commercial microprocessor, the 4-bit Intel , in , followed by its 8-bit microprocessor in AL-1, an 8-bit CPU slice that was expandable to bits.

The first microprocessors emerged in the early s and were used for electronic calculators , using binary-coded decimal BCD arithmetic on 4-bit words. Other embedded uses of 4-bit and 8-bit microprocessors, such as terminals , printers , various kinds of automation etc.

Affordable 8-bit microprocessors with bit addressing also led to the first general-purpose microcomputers from the mids on. Since the early s, the increase in capacity of microprocessors has followed Moore's law ; this originally suggested that the number of components that can be fitted onto a chip doubles every year.

With present technology, it is actually every two years, [6] and as a result Moore later changed the period to two years.

This section relies too much on references to primary sources. Please improve this section by adding secondary or tertiary sources. March Further information: Central Air Data Computer In , Garrett AiResearch who employed designers Ray Holt and Steve Geller was invited to produce a digital computer to compete with electromechanical systems then under development for the main flight control computer in the US Navy 's new F Tomcat fighter.

The design was significantly approximately 20 times smaller and much more reliable than the mechanical systems it competed against, and was used in all of the early Tomcat models. This system contained "a bit, pipelined , parallel multi-microprocessor ".

The Navy refused to allow publication of the design until Ray Holt's autobiographical story of this design and development is presented in the book: The Accidental Engineer.

From its inception, it was shrouded in secrecy until when at Holt's request, the US Navy allowed the documents into the public domain. Since then people[ who? Holt has stated that no one has compared this microprocessor with those that came later.The two types of interrupts are: i. What is the mode of operation in RS?

What are the modes of operation supported by ? They are used in the field of: I. Pin Diagram Explanation about all signals 3. Two bus lines are required, serial data line and serial clock line.

Logic — 0 to Logic — 1 change known as transition activated interrupt.